The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to nano-line semiconductor devices and methods of fabricating the same.
A semiconductor device, such as a metal-oxide semiconductor field-effect transistor (MOSFET), may be used as a switching device. Much research has been conducted to scale down the MOSFET in accordance with recent trends of a high integration density and a high performance of a semiconductor device. The scaling down of the MOSFET may improve the integration density of a semiconductor device, may improve a switching operating speed, and may improve a signal transfer speed by allowing shortening of distances between devices. However, conventional scaling-down of MOSFETs typically is based on a top-down approach that may be extended down to a nanometer level. A top-down approach, however, may present problems with respect to limits on length of a gate, a thickness of a gate insulating layer, an operating voltage, a junction depth of impurities, and the like.
Techniques for scaling down the size of the MOSFET have been described in US Patent Application Publication No. US2005/0121706 A1 entitled “Semiconductor Nano-Rod Devices” by Chen, et. al. According to Chen, et. al., a semiconductor nano-rod device having a cylindrical gate may be fabricated using a silicon on insulator (SOI) substrate. Specifically, a semiconductor layer formed on an insulating layer is patterned. The patterned semiconductor layer is formed to include a source region, a drain region and a channel region, and the planar areas of the source and drain regions may be greater than the planar area of the channel region. The insulating layer below the patterned semiconductor layer may be isotropically etched such that at least a lower portion of the channel region of the patterned semiconductor layer is exposed. As a result, the channel region of the patterned semiconductor layer may be entirely exposed. Then, a cylindrical gate structure may be formed to surround the channel region. However, as such a nano-rod device is realized using the conventional SOI substrate by a top-down approach, the scaling-down of the MOS transistor may be difficult.
An alternative technique for scaling down a MOSFET has been proposed. A carbon nano-tube can exhibit metal characteristics and/or semiconductor characteristics depending on a diameter and a shape of the carbon nano-tube. Research has been conducted toward developing a semiconductor device, such as a transistor, using a carbon nano-tube having semiconductor characteristics.